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Design of Analog CMOS Integrated Circuits; Mc-Graw Hill Inc.: New York, NY, USA, 2015. [Google Scholar]Hesham, O. Fast and accurate technique for comparator offset voltage simulation. Microelectron. J. 2019, 89, 91–97. [Google Scholar]Peng, X.; Gao, A.; Chen, Z.; Zhang, H.; Li, Y.; Cao, W.; Liu, X.; Tang, H. A Novel Comparator Offset Calibration Technique for SAR ADCs. In Proceedings of the 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, China, 6–8 June 2018. [Google Scholar]Zhang, Y.; Cai, J.; Li, X.; Zhang, Y.; Su, B. A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration. Microelectron. J. 2021, 116, 105–244. [Google Scholar] [CrossRef] Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 2. The common-mode buffer. Figure 2. The common-mode buffer. Figure 3. The symmetrical OTA. Figure 3. The symmetrical OTA. Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 6. Differential preamplifier with offset voltage. Figure 6. Differential preamplifier with offset voltage. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 8. Control logic circuit. Figure 8. Control logic circuit. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 10. The timing diagram of comparator offset trimming. Figure 10. The timing diagram of comparator offset trimming. Figure 11. The layout of the comparator. Figure 11. The layout of the comparator. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 13. Transient simulation test bench of the proposed comparator. Figure 13. Transient simulation test bench of the proposed comparator. Figure 14. Transient simulation curves of the proposed comparator (ripple = 30 μV). Figure 14. Transient simulation curves of
